Comparisons of Various Scan Delay Test Techniques
نویسندگان
چکیده
Chips that produce correct results under operating conditions are called good chips. Some good chips may fail structural tests applied via scan chains (also called overkill chips). A reduction in supply voltage (also called supply voltage droop) due to the resistance of power-ground network is called IR-drop. IR-drop is investigated as a potential cause of overkill. IR-drop may slow down the speed of a chip unnecessarily, which could result in failing the structural test even though the chip could operate correctly in normal operation (i.e., overkill). In order to reduce the switching activity, test patterns can be generated such that don’t-care bits are filled with the last significant bit (also called repeatfill test patterns). Our experiments show that repeat-fill test patterns reduce the occurrence of overkill by 58%, but increase the number of test escapes by 50%. A new technique to reduce potential overkill due to IR-drop is presented. Compared to the normal transition delay test set, the proposed technique was able to reduce the occurrence of overkill by 25% without increasing test escapes. The proposed test set has the same number of patterns as the normal transition delay test set while the repeat-fill test set has 2.3 times larger in test set length compared to the normal transition delay test set. Test time of proposed technique is 1.3 times longer than test time of the normal transition delay
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